Terminology and Bandwidth Accounting
FIG. 1 is a schematic diagram of an illustrative digital cross-connect switching system that includes sixteen 10 Gbps line cards 1A, a working switch card 1D, and a protection switch card 1E connected through a high-speed backplane 1C in one shelf 1F. The line cards 1A provide the primary inputs and outputs of the digital cross-connect switching system.
Each switch card 1E, 1F contains a 160 Gbps cross connect IC. The cross-connect IC on the working switch card 1D is illustrated as object 1B. If, in this example, all line cards 1A are the same, and each supports M/16 inputs and M/16 outputs for some number M, then the cross-connect IC 1B comprises an M×M switch matrix, as shown.
The protection switch card 1E and the working switch card 1D are identical. The traffic across the backplane is 640 Gbps since the line cards send and receive 160 Gbps of data to and from each of the two switch cards.
FIG. 2 is a three-dimensional view of the 160 Gbps switching system in FIG. 1. Not all line cards must be identical in the system. For example, there could be seven 20 Gbps line cards and eight 2.5 Gbps line cards in the system to utilize the full 160 Gbps switching capacity while taking fifteen out of sixteen line card slots 2A.
Suppose that the backplane 2C is designed to accommodate 1,280 Gbps of traffic. Each switch card in the expanded system can then cross-connect at most 320 Gbps of traffic. Several options are available to achieve this bandwidth.
1) FIG. 3A illustrates a monolithic cross-connect switch 300 having N inputs and N outputs, where N=KM for some value K. For example, the monolithic 160 Gbps cross-connect IC in each switch card 2D, 2E of FIG. 2 could be replaced with a monolithic 320 Gbps cross-connect IC, where K=2.
However, since the number of crosspoints increases quadratically as a function of bandwidth, such an IC is costly to manufacture. The industry is typically not willing to pay four times the price to get twice the bandwidth. The manufacturing cost of such a monolithic IC is particularly high if advances in IC fabrication technology lag bandwidth growth.
2) Parallel processing techniques, such as bit- or byte-slicing to scale the bandwidth, could be employed. For example, two nibble-sliced 160 Gbps cross-connect ICs can switch 320 Gbps data in parallel. See, for example, McKeown, N., et al., “The Tiny Tera: A Packet Switch Core”, Hot Interconnects V, Stanford University, August 1996, incorporated herein by reference.
FIG. 3B is a schematic diagram illustrating this technique. One cross-connect IC 55 processes the upper nibble of each byte while the other cross-connect IC 57 processes the lower nibble. This method additionally requires a slicer 51 to slice, and a reassembler 53 to reassemble, data between the line cards and the switch cards. If line cards perform slicing and reassembly, then only these line cards can communicate with the sliced cross-connects.
Legacy line cards that do not slice and reassemble data would have to be modified or replaced, an option that does not offer backward compatibility. A cross-connect bandwidth upgrade should involve upgrading the switch cards while preserving the line cards to be cost-effective.
If the switch card performs slicing and reassembly, then additional ICs are necessary to slice and reassemble the data there. Since all data links are high-speed links (typically at 2.5 Gbps line rate in 2002), this option doubles the number of these high-speed links on the switch card and triples the number of high-speed ports since the number of high-speed ports in the slicer and the reassembler is twice as many as that of the cross-connect ICs. As a result, this approach doubles the amount of high-speed link routing on the switch card and triples the power consumed by the high-speed ports.
3) A 320 Gbps cross-connect with multiple smaller cross-connect ICs could be implemented to form a Clos network but the resulting system is blocking for arbitrary multicast traffic and requires scheduling. See Clos, C., “A Study of Non-Blocking Switching Networks,” Bell System Technical Journal, vol. 32, 406-424, 1953, incorporated herein by reference.